1. Field of the Invention
The present invention relates to phase-locked loop systems which provide for selection between two or more reference signals for input, to the phase-locked loop.
2. Description of Related Art
A phase-locked loop circuit operates to provide an output signal that is synchronized in phase with a reference input signal. In systems requiring high reliability, such as systems providing network synchronization in communication networks that transmit time-multiplexed data, it is desirable to have a phase-locked loop with redundant reference inputs. In case the controlling reference input suffers a fault, the loop can be switched to one of the redundant inputs to reduce the impact of the reference input fault.
The process of switching from one reference input to another must be carried out without losing lock condition in the phase-locked loop. In the prior art there have been two topologies which could support more than one reference input. The first such prior art topology is shown in FIG. 1 and the second such prior art topology is shown in FIG. 2.
The topology shown in FIG. 1 relies on the use of an input signal selector 10 to select one of the redundant reference inputs, REF1, REF2, . . . REFM, to provide a single reference input on line 11 for the phase-locked loop. As is typical in the art, the phase-locked loop includes a phase detector 12 which supplies a phase error signal on line 13 to a filter 14. The output of the filter is a control signal on line 15. A voltage-controlled oscillator 16 receives the control signal and generates an output signal on line 17. The output signal is fed back through a feedback path which typically includes a frequency divider 18. The output of the frequency divider is a phase-locked loop feedback signal on line 19, which is supplied to the phase detector 12.
In the topology of FIG. 1, in order to provide a loss-of-lock free switching between inputs, some restrictions on the type of components used in the loop are created. In particular, due to switching glitches that occur at the output of the selector 10 during switching from one reference input to another, the phase detector 12 must be a "phase only" type detector. It cannot be a phase and frequency type detector as explained below.
A phase-only detector operates by measuring the phase difference between the closest pair of rising edges, or falling edges, in the reference input signal and the loop feedback signal within a range of 180 degrees. The phase only detector can allow false locks in specific ratios of the reference signal, such as the major harmonic frequencies; therefore, the VCO must have a narrow bandwidth to eliminate the possibility of locking up at one of the false lock frequencies. The phase and frequency detector, on the other hand, is a state machine that generates an output based on the history of rising edges, or falling edges. In particular, it generates an output based on a set of rising edges within a range of 360 degrees that is determined by the history of the signals. Because the phase and frequency detector does not suffer the possibility of a false lock, one can use a wider bandwidth VCO in the phase-locked loop.
By using a phase-only type detector in the topology of FIG. 1, the designer is assured that any switching glitches cause only minor perturbation in the signal entering the filter 14, and can thus be sufficiently filtered so that the control signal on line 15 does not swing in an amount that would cause a loss of lock condition.
The use of only phase detection, however, can cause a problem with "false" lock conditions if the VCO 16 has a wide operating frequency range. To prevent false locks, the VCO must have a narrow frequency range to the point where only one stable operating frequency occurs. This stable operating frequency must correspond to the "lock" frequency expected to be reached by the phase-locked loop. Thus, a more stable, and more expensive variety of VCO must be used. Phase-locked loops of this topology having a wide frequency range can be implemented; however, the VCO must be designed so that it operates in a number of selectable narrow sub-ranges to provide the wide range. This further increases the complexity and cost of the apparatus.
FIG. 2 illustrates the second prior art topology. In this apparatus, a separate phase-locked loop is used for each reference input, and selection between reference inputs is provided by selecting from the output of redundant phase-locked loops. Thus, as can be seen in FIG. 2, the first reference input REF1 is supplied as a input to a first phase-locked loop 20. Subsequent reference inputs such as REFM, are each supplied to a separate phase-locked loop 21. The output of the phase-locked loop 20 on line 22 is supplied as a first input to a selector 23. The output of the phase-locked loop 21 on line 24 is supplied as an Mth input to the selector 23. The reference select signal on line 25 controls the selector to provide on an output line 26, the active output signal.
The topology of FIG. 2 suffers from being hard-ware intensive, requiring as many phase-locked loop circuits as there are reference inputs. The complexity of the circuit is further increased by the design of the selector 23. The action of the selector must be synchronized with the selected signal so that switching glitches do not occur on the output line 26 which can cause system synchronization problems for the apparatus relying on that signal.
The topology of FIG. 2 does overcome the requirement for use of expensive VCOs by eliminating switching glitches prior to the phase detector. Thus the phase detector can be implemented as a phase and frequency detector that prevents the false lock condition.
It is desirable to provide a phase-locked loop that accepts two or more reference inputs and has the following features:
(1) provides for a selection between reference inputs without losing lock when the reference signals are substantially phase-synchronized, such as when generated by a common source.
(2) operates over a wide frequency range without danger of false locks.
(3) employs low complexity circuitry that can be implemented with low cost components, especially a low stability, inexpensive VCO chip.